Is General Embedded Ready for MLC NAND?

Posted by: Thom Denholm

Adoption by Industrial & Mil-Aero Promises Some Rewards & Major Issues MLC NAND is experiencing a high rate of adoption and within the consumer electronics sector - MP3 players, digital cameras, smart phones, flash cards and USB drives - it is everywhere you look. However, other embedded segments (industrial, automotive, military, aerospace, etc), are hesitating to take advantage of MLC's low-cost, high-density attributes. There are good reasons behind the cautious stance; these applications are often mission critical, have a low tolerance for failure, and are expected to perform consistently over a much longer lifespan than their counterparts in the nearly-disposable consumer world. These requirements are in direct conflict with some of MLC's known shortcomings: shorter lifespan, shorter data retention times, higher error rates, more complex (and consequently slower) error detection and correction. On the topic of lifespan, traditional single-level NOR parts are typically expected to endure up to 100,000 cycles, which could translate to 20 years of use in a typical embedded application.  Most MLC NAND is rated for 10,000 cycles, rendering these parts unusable in 2 years under the same use case.  While 2 years is a long time for many consumer grade products, it is unacceptably short for the vast majority of industrial products. Similarly, data retention requirements differ.  Traditional flash data retention rates have been 20 years, but recently some flash parts are being introduced with only a 10 or 15 year rating. Applications involving products with life times in the 10 year range need to consider such limitations. Lower erase cycle endurance is conceptually easy to manage: track high use areas and occasionally swap the data within those areas with a low use area. However, a major difficulty is brewing that involves how errors are introduced and the performance impact of detecting and correcting them. When writing pages within an erase block, disturb errors may be introduced, causing some number of bits to be flipped in pages other than the one being written to. The time required to read and verify the contents of the entire erase block can cause unacceptable delays, leading programmers to defer the detection until the next read operation, which may occur infrequently. Consequently, bit errors can exist in these "not written to" pages for a long time before they are detected. And the issues with MLC error rates will worsen, as each new generation of chips pushes the cell size down even further. Future generations of MLC NAND devices beyond the 35nm range may have to distinguish between only a few hundred electrons on each cell. With so few electrons, discerning among the multiple levels of charge in a cell will be a time-consuming, error-prone process. The somewhat obvious solution is to put in place a process to read and verify areas in the vicinity of writes in an attempt to detect disturb errors earlier.  A solution like this must be carefully balanced with the system performance requirements. MLC NAND has many compelling reasons for adoption, but until its challenges are successfully dealt with, it will not be broadly accepted by industrial, mil-aero, and automotive device designers as a viable replacement for tried and true technologies of SLC NAND and NOR. At Datalight, we are focused on easing many of the problems of MLC NAND. For more information on our intelligent flash management solutions, please visit our resourcespage.


Comments (0)

Add a Comment

Allowed tags: <b><i><br>Add a new comment: