The read, write and erase timing characteristics of flash hardware specifications are useful for comparing different products, but don't tell the whole story about what you will get from your real-world devices. When Flash memory is incorporated into a system, the performance of the system depends on a number of factors. One key factor that can reduce the effective performance of flash memory involves the shared bus topology of your system. Optimal flash performance depends on the speed and availability of the bus that connects the flash to the system. Also critical are the manner in which the operating system handles interrupts and whether the flash device is connected to the system's interrupt architecture. The published read, write, and erase timing characteristics of flash hardware specifications are useful for comparing different products, but don't tell the whole story about what you will get from your real-world devices. When Flash memory is incorporated into a system, the performance of the system depends on a number of factors in addition to the capabilities of the flash hardware. One key factor that can reduce the effective performance of flash memory involves the shared bus topology of your system. Optimal flash performance depends on the speed and availability of the bus that connects the flash to the system. For example, if your flash shares a bus with parts that operate at slower clock speeds, the timing of the accesses to the flash part may be extended to match. On the other hand, your flash part may be competing for bus availability with other demanding high-speed system components. RAM memory, network interfaces, and LCD screens are demanding components that can compete with flash for bus and CPU bandwidth. The use of certain features of the processor and operating system, such as DMA and caching, can have a similar impact. As more components, peripherals, and device drivers are added to the system, more opportunities arise for the bus to be shared. The proliferation of high performance audio and video features, now common on mobile devices, can further tax a shared bus system on a general purpose chipset. For this reason special-purpose chipsets designed for a specific application, as well as tuning the characteristics of your flash management software to meet your specific needs, will generally enable higher levels of flash performance. Well designed hardware bus topology can alleviate the issue of shared bus contention, yet other factors may still impact flash memory performance. Even if the flash part has full speed access to the processor's external bus, the availability of the CPU to service that bus is still a question. Bus arbitration may take CPU cycles away from the flash bus in favor of other system busses or internal accesses. Operating system timer interrupts and other peripheral device driver interrupts can interfere with flash software operations, as can a CPU that is simply overloaded by running complex applications. Also critical are the manner in which the operating system handles interrupts and whether the flash device is connected to the system's interrupt architecture. Some flash is connected to processors in such a way that the signal generated by the flash is connected to a GPIO, or not connected at all. This may have little impact on flash performance, but it will limit the ability of the CPU to execute other flash-related software, such as garbage collection, or even unrelated tasks. Additionally, many systems have an explicit or implied interrupt priority that must be considered at the system level. Responsiveness requirements of all interrupt-driven components in the system must be carefully weighed against the desire to maximize flash performance. An equally significant factor affecting flash performance that might be easily overlooked is the flash management software itself. There is a necessary amount of overhead inherent in running software to manage your flash memory, and there are some complex operations that the software needs to accomplish well in order to optimize flash performance. The software provided by your flash vendor may or may not provide satisfactory performance for your particular application. While flash memory often appears to the end user like a virtual hard drive, the underlying technology is quite different and presents certain challenges. Flash management software can do more than bad block management and wear leveling, it can increase the effective performance of the flash part by addressing these challenges:
- Flash performance can be impeded by the need for a slow erase operation before writing new data, but software that intelligently performs background garbage collection during idle time can solve that problem.
- Fragmented data can degrade performance in applications such as streaming media from NAND memory, but compaction software that de-fragments the data can improve performance in these situations.
- With some algorithms, throughput is maximized for performance until a percentage of the flash memory is used, at which point performance can degrade. The percentage of the flash that is used before performance suffers can be tuned in some implementations, by allowing the system designer to reserve a specified amount of 'cushion' of unused memory.
- In some solutions, maintenance operations such as garbage collection can preempt high-priority read requests. Implementations that make careful use of multithreading operating systems' capabilities to manage this issue can reduce read latency by orders of magnitude.
Several factors will affect the performance of flash memory in your real-world system, some of which may be beyond your control. Chipset hardware and system bus topology decisions may have been made already. No matter whether your hardware is specially designed for your application or you are using a general-purpose hardware design, though, the effective performance of your flash memory can be improved through software methods. Datalight FlashFX is a multithreading memory management software solution that enables garbage collection, data compaction, memory cushion, and high priority read interrupts to allow the highest real-world flash performance your hardware configuration can support.